[zircon][arch/x86]: Enumerate PCID, add basic definitions

PCID, "Processor Context ID", are a TLB entry and paging structure cache
entry tagging mechanism introduced in the Intel Westmere family of CPUs.
PCID allows entries from multiple address spaces to remain live in both
classes of caches, possibly improving performance in ping-pong types of
applications.

PCIDs may be interesting in zircon to implement separate kernel/user
address spaces, to mitigate certain speculative execution information
leaks (ex: 'Meltdown'); PCID may allow us to avoid invalidating all
translation caches on mode switches while separating kernel / user
mappings.

Introduce global bit that tracks whether PCIDs and INVPCID are available
and a helper to enable PCIDs in CR4. Add constants for PCID width and
the PCID save control bit in CR3.

ZX-1526
ZX-1528
ZX-1529

Tested: Built.

Booted on qemu w/o PCID: printed pcid_good=0.
Booted on qemu w/ PCID but without INVPCID: printed pcid_good=0
Booted on qemu w/ PCID and INVPCID: pcid_good=1
Booted on qemu on AMD f15h cpu=host: pcid_good=0

Change-Id: I6e2ed3c9656f420e5321d14013efac90dd33ce1d